To provide a method and a system for designing a semiconductor integrated circuit device which method and system each enable suppression of waveform rounding below a specific limit value in an early stage of development of the semiconductor integrated circuit device without performing delay calculation.
The resistance Rpath of a wiring path from the output terminal of an object circuit cell to a next-stage circuit cell is compared with permissible longest wiring resistance RtL with which the object circuit cell can be driven and when Rpth is not larger than RtL (S4: YES), the sum Rtotal of the resistance of a wiring load of a net is compared with RtL, when Rtotal is not larger than RtL (S5: YES), it is decided that the next-stage circuit cell can be driven below a prescribed waveform rounding limit value. When Rtotal is larger than RtL (S5: NO), the effective resistance Rw of the wiring load is compared with permissible longest wiring effective resistance RwL and when Rw is not larger than RwL (S6: YES), it is decided that the waveform rounding of the next-stage circuit is less than the prescribed limit value.
YONEDA TAKASHI
FUJITA MIYAKO
WAKITA MAKOTO
FUJITSU VLSI LTD
Next Patent: SYSTEM AND METHOD FOR TIMING ANALYSIS