METHOD AND SYSTEM FOR INCREASING PARALLELISM OF SYSTEM MEMORIES OF MULTIPROCESSOR COMPUTER SYSTEM

Japanese Patent JP2575598

B2

PURPOSE: To simultaneously change reference bits and change bits through a plurality of processors and to increase the parallelism of system memories.
CONSTITUTION: This system includes the system memories, processors and a TLB(translation lookaside buffer) which converts an effective address into a real memory address included in a system memory. Then a plurality of page table entries including a plurality of fields that can be individually accessed, effective addresses of a specific system memory position and the relative real memory addresses of a selected system memory position are offered in a page table included in the system memory. The reference bits are offered in the fields of every page table entry which can be individually accessed and then used to indicate whether the relative system memory position is accessed for the read/write operations. In the same way, the change bits are offered and used to indicate whether the relative system position is corrected by a write operation. Then plural processors simultaneously change the reference and change bits to increase the parallelism of system memories.

JEEMUZU EI KAARE
JON ESU MYUUIKU
RICHAADO AARU EERAA
EDOWAADO JEI SHIRYA

JP31556393A

January 29, 1997

December 15, 1993

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INTAANASHONARU BIJINESU MASHIINZU CORP

G06F15/16; G06F12/10; G06F15/177; (IPC1-7): G06F15/163

JP2162439A
JP4306750A

Kiyoshi Goda (2 outside)

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