Title:
METHOD, SYSTEM, PROGRAM, RECORDING MEDIUM, MASK, AND EQUIPMENT FOR IMPROVING YIELD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP2007150316
Kind Code:
A
Abstract:
To provide a method of improving an yield of a semiconductor integrated circuit device which is maximized by correcting a layout of interest based on a fault rate of a design rule.
A method of improving an yield of semiconductor integrated circuit device comprises: a step of calculating a fault rate of a design rule based on multiple fault rates of corresponding multiple experimental design rule values and on the number of features in a layout of interest corresponding to the multiple experimental design rule values, respectively; and a step of correcting the layout of interest based on the fault rate of the design rule. This method can design a layout with a maximized yield.
Inventors:
BAE CHOEL-HWYI
KWON SANG-DEOK
BAEK GWANG-HYEON
KWON SANG-DEOK
BAEK GWANG-HYEON
Application Number:
JP2006317697A
Publication Date:
June 14, 2007
Filing Date:
November 24, 2006
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO LTD
International Classes:
H01L21/82; G06F17/50
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Previous Patent: JP2007150315
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