To manufacture a PLL circuit with proper examination step flow and a minimum examination time.
The present invention relates to a system and method for configuring a dividing ratio of a phase-locked loop (PLL) which does not require the phase-locked loop circuit to lock. In one embodiment, the method includes inducing a substantially minimum or substantially maximum frequency output from a voltage-controlled oscillator (VCO), and configuring a divider with a corresponding dividing ratio. The method may include grounding an input voltage to the VCO. Alternatively, the method can include manipulating inputs to a charge pump providing input to the VCO. The charge pump inputs may be manipulated directly or through a phase-frequency detector providing input to the charge pump and adapted to receive additional input signals.
| JPS63226116A | 1988-09-20 | |||
| JPH10271001A | 1998-10-09 | |||
| JP2001135038A | 2001-05-18 | |||
| JP2001084709A | 2001-03-30 |
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
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