METHOD FOR WIRING AND DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

METHOD FOR WIRING AND DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JPH06163693

Kind Code:

A

Abstract:

PURPOSE: To satisfy connection requirements between a bump and an input terminal or an output terminal of an I/O cell inside a chip without being affected by the result of wiring layout design inside a chip.

CONSTITUTION: A unit area is set to each cell registered in a cell library in such a fashion that it may not interfere with chip inside wirings, and what is more, the unit area is designed to cross the cell. When having formed a row of cells 40, which are laid out as described above, the unit areas are shaped up in a continuous band, thereby securing a dedicated area 33. After cell-to-cell wiring layout design inside the chip is completed, the wirings are installed in the dedicated area 33, thereby designing wirings between a bump and an input terminal or an output terminal of an I/O cell.

Inventors:

SUMI SATORU

Application Number:

JP31368392A

Publication Date:

June 10, 1994

Filing Date:

November 24, 1992

Export Citation:

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Assignee:

FUJITSU LTD

International Classes:

H01L21/82; H01L21/321; H01L21/60; (IPC1-7): H01L21/82; H01L21/321

Attorney, Agent or Firm:

Matsumoto Shinkichi

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