Title:
乗算器を利用しない有限インパルス応答フィルタを実装する方法および装置
Document Type and Number:
Japanese Patent JP5108022
Kind Code:
B2
Abstract:
A finite impulse response filter is implemented as a sum of individual component, running-sum filters. The sum of all of the component filters required for a desired filter response is calculated in an accumulator and only the component filters' update terms, which are the difference between a new and an old discarded sample, is calculated for each component filter. A desired impulse response is decomposed into a sum of rectangular impulse responses of equal height, each of which implemented as a running sum requiring a subtraction and an addition. Using circuits running at a multiple of the sampling clock, multiple running sums may be implemented on the same hardware. A whole filter of arbitrary impulse response shapes and lengths may be implemented using memory and two arithmetic units. Two or more such filters may be cascaded to obtain a better approximation of the desired frequency characteristic. The invention saves significant chip resources and manufacturing costs.
Inventors:
Alexandre Radu
Application Number:
JP2009540417A
Publication Date:
December 26, 2012
Filing Date:
December 04, 2007
Export Citation:
Assignee:
Hitachi Aloka Medical Co., Ltd.
International Classes:
H03H17/06
Domestic Patent References:
| JP7058784A |
Foreign References:
| WO2005109640A1 |
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida
Jun Ishida