Title:
シリコン単結晶基板中に、MOSFETデバイスのための接合を形成するための方法
Document Type and Number:
Japanese Patent JP4948785
Kind Code:
B2
Abstract:
A structure and method of fabrication for MOSFET devices with a polycrystalline SiGe junction is disclosed. Ge is selectively grown on Si while Si is selectively grown on Ge. Alternating depositions of Ge and Si layers yield the SiGe junction. The deposited layers are doped, and subsequently the dopants outdiffused into the device body. A thin porous oxide layer between the polycrystalline Ge and Si layers enhances the isotropy of the SiGe junctions.
Inventors:
Kevin Cock Chan
Robert Jay Miller
Erin Sea Jones
Atul Ajumera
Robert Jay Miller
Erin Sea Jones
Atul Ajumera
Application Number:
JP2005147746A
Publication Date:
June 06, 2012
Filing Date:
May 20, 2005
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/225; H01L29/78; C30B1/00; H01L21/20; H01L21/205; H01L21/331; H01L21/336; H01L21/36; H01L21/8222; H01L29/08; H01L29/165; H01L21/316
Domestic Patent References:
| JP5013347A | ||||
| JP4127522A | ||||
| JP11087708A | ||||
| JP57128022A | ||||
| JP8139017A |
Foreign References:
| WO2004034458A1 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi