Title:
半導体製造歩留まりを向上させるための方法
Document Type and Number:
Japanese Patent JP7022111
Kind Code:
B2
Abstract:
Embodiments of the present disclosure provide systems and methods for enhancing the semiconductor manufacturing yield. Embodiments of the present disclosure provide a yield improvement system. The system comprises a training tool configured to generate training data based on receipt of one or more verified results of an inspection of a first substrate. The system also comprises a point determination tool configured to determine one or more regions on a second substrate to inspect based on the training data, weak point information for the second substrate, and an exposure recipe for a scanner of the second substrate.
Inventors:
Fan way
Application Number:
JP2019506496A
Publication Date:
February 17, 2022
Filing Date:
August 14, 2017
Export Citation:
Assignee:
ASM L Netherlands B.V.
International Classes:
H01L21/02; G03F7/20; G05B19/418; H01J37/22
Domestic Patent References:
| JP2010514226A | ||||
| JP2011040661A | ||||
| JP2013074294A | ||||
| JP2011176309A | ||||
| JP2013058654A | ||||
| JP2013084731A |
Attorney, Agent or Firm:
Yoshiyuki Inaba
Toshifumi Onuki
Akihiko Eguchi
Kazuhiko Naito
Toshifumi Onuki
Akihiko Eguchi
Kazuhiko Naito