Title:
データビットを並列に符号化する方法および装置
Document Type and Number:
Japanese Patent JP5886235
Kind Code:
B2
Abstract:
A method and apparatus for encoding multiple bits in parallel wherein outputs arc generated recursively. During each clock cycle, the encoder (1500) processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units (1104 to 1106), which are then each uniquely addressed to provide data to parallel encoders.
Inventors:
James Wy Heart
Michael A. Howard
Robert Jay Fuchs
Michael A. Howard
Robert Jay Fuchs
Application Number:
JP2013083336A
Publication Date:
March 16, 2016
Filing Date:
April 11, 2013
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
H03M13/27; H03M13/00; H03M13/29; H04L1/00
Domestic Patent References:
| JP11074800A | ||||
| JP2000286722A |
Foreign References:
| WO2000052834A1 | ||||
| WO2000060751A1 | ||||
| WO2002069504A2 | ||||
| WO2000060751A1 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori