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Title:
遅延ロックループ及び位相ロックループに関する方法及び装置
Document Type and Number:
Japanese Patent JP2013534744
Kind Code:
A
Abstract:
A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.

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Inventors:
Mosalicanti, Plavin
Kurdish, Nasser A.
Mozak, Christopher Pee.
Application Number:
JP2013513253A
Publication Date:
September 05, 2013
Filing Date:
May 27, 2011
Export Citation:
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Assignee:
Intel Corporation
International Classes:
H03L7/081; G11C11/407; G11C11/4076; H03K5/13; H03L7/00; H03L7/08
Domestic Patent References:
JP2007166163A2007-06-28
JPH08147967A1996-06-07
JP2001250382A2001-09-14
JPH08223038A1996-08-30
JPH1051299A1998-02-20
JP2006261898A2006-09-28
JP2007243877A2007-09-20
JPH04145722A1992-05-19
JP2006511899A2006-04-06
JP2000022524A2000-01-21
JP2001217682A2001-08-10
JP2005070967A2005-03-17
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki



 
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