Title:
複数の通信リンクとリモートダイレクトメモリアクセスプロトコルとの統合のための方法および装置
Document Type and Number:
Japanese Patent JP2005508032
Kind Code:
A
Abstract:
In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.
Inventors:
Corn Leslie Di.
Won Michael Kay.
Won Michael Kay.
Application Number:
JP2003539249A
Publication Date:
March 24, 2005
Filing Date:
October 21, 2002
Export Citation:
Assignee:
SUN MICROSYSTEMS INCORPORATED
International Classes:
G06F1/32; G06F9/30; G06F9/38; G06F9/46; G06F12/00; G06F11/10; G06F12/08; G06F12/16; G06F13/00; G06F13/14; G06F13/16; G06F13/38; G06F15/16; G06F15/167; G06F15/173; G06F15/78; G06F21/00; G09C1/00; G11C11/4074; H04L12/56; H04L29/06; (IPC1-7): G06F12/16; G06F15/16; G06F15/167; G06F15/78
Attorney, Agent or Firm:
Meisei International Patent Office