Title:
低電力状態で動作する集積回路でキャッシュコヒーレンシを維持する方法および装置
Document Type and Number:
Japanese Patent JP4083816
Kind Code:
B2
Abstract:
A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.
Inventors:
Kardatch, James Py
Holligan, john
Ecumbalam, Lavre
Nakanishi, Tosaku
Chan, Chin-Han
Senik, Boris S
Holligan, john
Ecumbalam, Lavre
Nakanishi, Tosaku
Chan, Chin-Han
Senik, Boris S
Application Number:
JP54803598A
Publication Date:
April 30, 2008
Filing Date:
January 27, 1998
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/08; G06F1/04; G06F1/32
Domestic Patent References:
| JP10301659A | ||||
| JP9097128A | ||||
| JP8297607A | ||||
| JP5233275A | ||||
| JP4143819A |
Foreign References:
| US5530932 |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa