Title:
JTAGを用してASIC内のメガセルを試験する方法と装置
Document Type and Number:
Japanese Patent JP3698166
Kind Code:
B2
Abstract:
Specially modified JTAG test circuitry is used to provide test inputs and outputs for vendor supplied megacells with buried I/Os within an integrated circuit chip. A multiplexer or similar circuit is used to alternatively select between a JTAG boundary scan output or a megacell circuit test output in response to JTAG instructions within an instruction register. Additionally, a multiplexer or similar circuit is used to alternatively select between an input pin or normal circuitry for input to a megacell's buried input. Furthermore, an AND or OR gate is used to allow test inputs to a megacell, which are normally tied either high or low, to be controlled by an input pin when in the special JTAG test mode. In this manner, test vectors applied at test inputs to the megacell circuitry result in test outputs to the megacell circuitry being provided on output pins of the integrated circuit without requiring additional input and/or output pins that are solely operational as test inputs or outputs to the megacell circuitry.
Inventors:
Mote, Randall El., Juniors
Application Number:
JP50112397A
Publication Date:
September 21, 2005
Filing Date:
June 06, 1996
Export Citation:
Assignee:
Samsung Electronics Company, Limited
International Classes:
G01R31/3185; G01R31/28; (IPC1-7): G01R31/28
Domestic Patent References:
| JP2245943A | ||||
| JP4357477A | ||||
| JP458172A | ||||
| JP4276570A |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu