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Title:
チップを積層するために、そしてチップ及びウェハを接合させるために有用な方法及び材料
Document Type and Number:
Japanese Patent JP5656349
Kind Code:
B2
Abstract:

To provide materials, and methods that use such materials, that are useful for forming chip stack structure, chip and wafer bonding and wafer thinning.

The surface of a substrate 10 is coated by a photosensitive polymer, having a weight-average molecular weight of 10,000-50,000, after removing the volatiles, and a development pattern is obtained. In the development process, a part 20 where the polymer is not removed, and gap parts 30, 40 where the polyMer is removed are formed and bake curing is performed. A bonding pad 50 is exposed. Another structure, such as lamination, is formed using the coated substrate by cure process. The cure process continues bridge, for example, in the first cure step and completes bonding at higher temperature in a second cure step.

COPYRIGHT: (C)2009,JPO&INPIT


Inventors:
クリス アパニアス
ロバート エー. シック
ヘンドラ エヌジー
アンドリュー ベル
ウェイ チャン
フィリップ エス. ニール
Application Number:
JP2008241926A
Publication Date:
January 21, 2015
Filing Date:
September 22, 2008
Export Citation:
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Assignee:
プロメラス, エルエルシー
International Classes:
H01L25/065; C08F32/00; H01L25/07; H01L25/18
Attorney, Agent or Firm:
Yasuhiko Murayama
Masatake Shiga
Takashi Watanabe
Shinya Jitsuhiro