To reduce the maximum current consumption of a data processor or a whole single chip micro computer by time-divisionally operating the micro processor and a peripheral equipment.

A clock generation circuit 3a stops the generation of a clock CKI with a control signal CNTa from a sleep flag 15. A clock generation circuit 3b is started with a control signal CNTb from an AND gate 22 which AND- operates the state of the sleep flag 15 and an operation flag 21 and a clock CK2 is supplied to the peripheral equipment 2. Thus, the peripheral equipment 2 starts the operation. When a processing terminates in the peripheral equipment 2, the peripheral equipment operation flag 21 is automatically reset. The control signal CNTa outputted from the sleep flag 15 changes to a low level, the clock generation circuit 3a is started and the clock CK1 is supplied and the micro processor 1 resumes the operation.