Title:
MICROCHIP AND LAMINATION METHOD OF PDMS SUBSTRATE AND COUNTER SUBSTRATE
Document Type and Number:
Japanese Patent JP3918040
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a microchip showing sufficient lamination strength only by self-attraction properties without relying on the permanent adhesion of PDMS regardless of the kind of a substrate to be used.
SOLUTION: In the microchip composed of at least one sheet of polydimethylsiloxane (PDMS) substrate and the counter substrate laminated to the PDMS substrate, a negative-pressure pipeline is continued to the part near to the outer peripheral edge on the side of the lamination surface of the PDMS substrate to be formed into an annular shape. By evacuating and sucking the air inside the negative pressure pipeline of the PDMS substrate, the PDMS substrate is vacuum sucked.
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Inventors:
Inoue Masao
Application Number:
JP2004059112A
Publication Date:
May 23, 2007
Filing Date:
March 03, 2004
Export Citation:
Assignee:
Aida Engineering Co., Ltd.
International Classes:
G01N35/08; B81B1/00; G01N37/00; (IPC1-7): G01N35/08; B81B1/00; G01N37/00
Domestic Patent References:
| JP2003121311A | ||||
| JP2002085961A | ||||
| JP2004521323A | ||||
| JP2004028589A | ||||
| JP2001157855A |
Foreign References:
| WO2002044412A1 |
Attorney, Agent or Firm:
Kajiyama Hiroshi
Fujio Yamamoto
Fujio Yamamoto