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Patent Searching and Data


Title:
MICROCOMPUTER
Document Type and Number:
Japanese Patent JPH0358207
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption as a whole by providing a selection circuit which selects and outputs one of plural system clocks from a frequency division circuit, and enabling the system clock supplied to each functional unit to be selected.

CONSTITUTION: An oscillation circuit 1 oscillating with a prescribed frequency, the frequency division circuit which frequency-divides an oscillation clock from the oscillation circuit 1 and generates plural system clocks CL1-CL4, and the select9ion circuits 31A-31N which select and output one of the system clocks CL1-CL4 with a write signal WR from a CPU 4 according to written data are provided. Furthermore, plural functional blocks 3A-3N provided with internal circuits 32A-32N operated with the system clocks outputted from the selection circuits 31A-31N correspondingly, and perform prescribed functions are provided. Thereby, it is possible to supply the system clock suitable for each functional unit, and to reduce the power consumption as a whole.


Inventors:
KANAI TETSUO
Application Number:
JP19545489A
Publication Date:
March 13, 1991
Filing Date:
July 27, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F1/08; (IPC1-7): G06F1/08
Domestic Patent References:
JPH01180024A1989-07-18
JPS61136115A1986-06-24
JPS5734245A1982-02-24
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)