PURPOSE: To reduce power consumption as a whole by providing a selection circuit which selects and outputs one of plural system clocks from a frequency division circuit, and enabling the system clock supplied to each functional unit to be selected.
CONSTITUTION: An oscillation circuit 1 oscillating with a prescribed frequency, the frequency division circuit which frequency-divides an oscillation clock from the oscillation circuit 1 and generates plural system clocks CL1-CL4, and the select9ion circuits 31A-31N which select and output one of the system clocks CL1-CL4 with a write signal WR from a CPU 4 according to written data are provided. Furthermore, plural functional blocks 3A-3N provided with internal circuits 32A-32N operated with the system clocks outputted from the selection circuits 31A-31N correspondingly, and perform prescribed functions are provided. Thereby, it is possible to supply the system clock suitable for each functional unit, and to reduce the power consumption as a whole.
JPH01180024A | 1989-07-18 | |||
JPS61136115A | 1986-06-24 | |||
JPS5734245A | 1982-02-24 |