PURPOSE: To reduce the number of digital comparators by successively comparing plural correction addresses stored in a memory with the address outputted from a program counter with a high frequency and changing a program instruction in accordance with the coincidence signal outputted for coincidence between them.
CONSTITUTION: A comparing means (coincidence discriminating circuit) 8 successively compares plural correction addresses with the address outputted from a program counter 3 by the timing of a second timing signal from a timing generating circuit 5 and outputs the coincidence signal at the time of coincidence between them. A program instruction changing means 9 changes the program instruction by the coincidence signal of the coincidence discriminating circuit 8. That is, the changed program is executed or an interrupt signal is generated. Thus, it is unnecessary to provide a digital comparator for each of all correction addresses, and it is sufficient if one coincidence discriminating circuit 8 is provided.
ISHIMARU HISAAKI
MIYAZAKI SATOSHI
MIYASAKA TETSUO
KOBAYASHI KAZUTADA
KAWAMURA SHOJI
