Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MICROCOMPUTER
Document Type and Number:
Japanese Patent JPS6271472
Kind Code:
A
Abstract:

PURPOSE: To scale down the size of a chip, and to improve the efficiency of the design of a mask by frequency-dividing a timing clock by a plurality of flip-flops, inputting an output from the timing clock to a logic circuit section and driving an output buffer section by an output generated in a time division manner.

CONSTITUTION: Flip-flops 1∼3 frequency-divide a timing clock generated in a microcomputer. Outputs from the flip-flops 2, 3 are inputted to a logic circuit 4, and outputs are generated at output terminals for the logic circuit in succession in a time division manner. These outputs are inputted to output buffer sections 9∼12 through AND gates 5∼8. Outputs from these output buffer sections 9∼12 are each connected to the outside through external connecting terminals 19∼22. Currents flowing in from the external connecting terminals 19∼22 flow out to the outside from an external connecting terminal 24 together with the supply currents of other circuits through a Vss line 23 in a chip.


Inventors:
YAMASHITA HIDEKAZU
TERAI HARUO
MOCHIDA NORIHITO
Application Number:
JP20912385A
Publication Date:
April 02, 1987
Filing Date:
September 20, 1985
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H02M1/08; G06F15/78; (IPC1-7): G06F15/06; H02M1/08
Domestic Patent References:
JPS53110360A1978-09-27
Attorney, Agent or Firm:
Akira Kobiji (2 outside)