Title:
マイクロコントローラ
Document Type and Number:
Japanese Patent JP4152795
Kind Code:
B2
Abstract:
It is an object to increase a speed of a CPU operation irrespective of an operation speed of a peripheral circuit and to prevent an increase in power consumption from being thereby caused. A clock generating circuit ( 10 ) generates two clocks having phases which are equal to each other, that is, a CPU clock (CLKCPU) and a bus clock (CLKBUS). A BIU (bus interface unit) ( 51 ) controls a code bus based on the CPU clock (CLKCPU) and controls a peripheral bus based on the bus clock (CLKBUS). The clock generating circuit ( 10 ) switches a frequency of each of the CPU clock (CLKCPU) and the bus clock (CLKBUS) depending on an operation mode of an MCU. For example, a speed of the CPU clock (CLKCPU) is set to be higher than that of the bus clock (CLKBUS) in order to carry out a high-speed operation of a CPU. Also in that case, the phases of both clocks are equal to each other. Consequently, the code bus and the peripheral bus in the BIU ( 51 ) can easily be controlled.
Inventors:
Hiroki Takahashi
Kazuo Nakamura
Kazuo Nakamura
Application Number:
JP2003100434A
Publication Date:
September 17, 2008
Filing Date:
April 03, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G06F15/78; G06F1/04; G06F1/08; G06F1/10; G06F1/32
Domestic Patent References:
| JP2002108490A | ||||
| JP2002082904A |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita