Title:
MICROPROCESSOR DEVICE FOR SUPPORTING BURST-ENABLED AND CACHE-DISABLED MEMORY ACCESS
Document Type and Number:
Japanese Patent JP3886189
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a device using a microprocessor capable of improving the performance of memory access by executing a burst-enabled access to a cache-disabled memory position.
SOLUTION: The device has a memory address space and an I/O address space. When the microprocessor 5 outputs a cache request signal and an I/O request control signal, a burst access is executed to an area of a main memory 20 to which a cache access is suppressed. A memory controller 10 interprets the burst access as a burst request to a cache-disabled memory position, outputs a cache response control signal to indicate the permission of the burst access and executes a burst memory access. Then the memory controller 10 responds to a burst access to a cache-disabled memory space by a burst response signal different from the cache response control signal.
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Inventors:
Jonathan Eich Ciel
Ashwini Kei Nanda
Ian Chen
Stephen Dee. Kruger
Ashwini Kei Nanda
Ian Chen
Stephen Dee. Kruger
Application Number:
JP33713296A
Publication Date:
February 28, 2007
Filing Date:
December 17, 1996
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G06F12/08; G06F13/28; (IPC1-7): G06F12/08; G06F12/08
Domestic Patent References:
| JP6348593A | ||||
| JP7114469A | ||||
| JP6501586A | ||||
| JP4293134A |
Foreign References:
| WO1992000590A1 |
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu
Hajime Asamura
Hayashi Zouzo
Kuniaki Shimizu