PURPOSE: To hold a state that is set right before the execution of an instruction is interrupted by cutting off the clock signal inputted to a timer and stopping the operation of the timer during a debugging job.

CONSTITUTION: When the execution of an instruction is stopped during a break or single step operation, one of both inputs of a 2-input OR gate 13 is set at a high level. Thus an S RFF 14 is set and the output 17 of the FF 14 is set at a high level. Then the output of a 2-input NOR gate 18 is set at a low level. As a result, the output of a 2-input AND gate 19 is set at a low level regardless of the state of a system clock 20. Then a timer 1 stops its time counting action. When a system is reset from a debugging action, a processor 3 sets the reset input 16 of the FF 14 at a high level and resets the FF 14. As a result, the outputs of the FF 14 and the gate 18 are set at low and high levels respectively. Thus the timer 1 can restarts its time counting action.