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Patent Searching and Data


Title:
MICROPROCESSOR USING N-MOS INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5880721
Kind Code:
A
Abstract:

PURPOSE: To reduce the power consumption and to maintain the speed of an arithmetic process, by providing a power supply ON/OFF control circuit between a microprocessor and a main power source and therefore ensuring a connection of the main power source by means of a working interruption to the microprocessor and turning off the main power source with the arithmetic stop signal.

CONSTITUTION: A microprocessor MPU is formed with an N-MOS IC, and a power supply ON/OFF control circuit PCC is provided between a power supply terminal VCC and a main power source E of the MPU. A transistor TR and an FF are provided to the circuit PCC, and the FF is reset by the start signal I supplied from an input/output control circuit IOC. Thus the TR conducts to supply the voltage to a clock oscillator CLK, a program memory PM, etc. At the same time, the FF is set by the arithmetic end signal H when an operation of the MPU is over. Thus the TR is made nonconductive to cut off the power supply to the MPU and other devices. As a result, the power consumption is reduced.


Inventors:
YASUNAGA SADAFUMI
Application Number:
JP17953681A
Publication Date:
May 14, 1983
Filing Date:
November 09, 1981
Export Citation:
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Assignee:
PILOT PEN CO LTD
International Classes:
H02J1/00; G06F1/32; G06F15/78; (IPC1-7): G06F15/06
Attorney, Agent or Firm:
Eisuke Suzuki