PURPOSE: To attain the transfer of data in the same bus width of a processor and in the least bus cycle of the processor by carrying out the transfer of data directly via a data control part and with no intervention of an execution control part.

CONSTITUTION: A data control part 102 secures the interface of an external data bus 101 which secures the direct connection between a processor and its external memory. An access control part 103 applies the access information to be given to the bus 101, i.e., a data access request signal REQ 107 to be given to the part 102 and a signal LENZ 108 with which the part 103 informs the part 102 of a fact that the remaining length of the block transfer is equal to 0 to the part 102. The part 102 outputs a signal RDY 109 to the part 103 to show that the transfer of data is possible. An execution control part 104 outputs a processor start signal BGN 110, and the part 102 outputs the end signals FIN 111 to both parts 103 and 104 to show the end of the transfer of blocks.