PURPOSE: To simplify the improvement of the microprocessor by providing two frequency divider multipliers generating clock signals dividing or multiplying independent reference clock signals based on the control of a processing unit.

CONSTITUTION: A microprocessor 1 is provided with two frequency divider multipliers 2a and 2b using PLLs, which accept reference clock signals 9 from an oscillator 3. A frequency divider multiplier 2a divides or multiplies the reference clock signal 9 into the specified frequency by accepting a control signal 7 from a processing unit 6, supplying them as internal clock signals 5 to the processing unit 6. A frequency divider multiplier 2b accepts a control signal 8 from the processing unit 6 and divides or multiplies the reference clock signal 9 into the frequency being the same as or dissimilar to the internal clock signal 5, outputting it as an external clock signal 4 to external peripheral circuits. Thus, the correspondence for the high-speed processing can be attained.