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Patent Searching and Data


Title:
MICROPROGRAM MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS59121547
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of a program loop due to the generation of a memory error in an error relieve routine by storing duplicatedly the error relieve routine to a memory and selecting the program operation alternately at the generation of error.

CONSTITUTION: When a program stored in a memory 14 is read on a decoder register 20, the normality of the contents is checked by a memory error detecting circuit 40 by the method such as parity check, and when an error is found out, the contents of a memory address register 41 or 42 storing a head address of the error relieve routine are selected switchingly by a changeover switch 43, contents of an address register are inputted to a branching condition discriminating section 30, and contents of the address 41 or 42 are set and branched to an address register 16 by a next address deciding section 18 forcibly. A changeover switch 43 stores the previously outputted side and selects alternately the stored contents by a signal of the memory error detecting circuit 40.


Inventors:
MATSUSHIMA HITOSHI
Application Number:
JP23062982A
Publication Date:
July 13, 1984
Filing Date:
December 28, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/22; G06F11/00; (IPC1-7): G06F9/22; G06F11/00
Attorney, Agent or Firm:
Koshiro Matsuoka