Title:
MICROSTRUCTURE FLATTENING METHOD
Document Type and Number:
Japanese Patent JPH07221082
Kind Code:
A
Abstract:
PURPOSE: To planarize microstructure with accuracy and cleanses by covering a material layer so as to bury the microstructure and measuring the thickness of the material layer and forming a residence time versus position map and removing the material with plasma auxiliary chemical etching based on this map. CONSTITUTION: A planarized layer 18 is formed on a surface 12 so as to cover a protrusion 16, thereby providing a relatively flat surface 20. The layer 18 is an oxide, such as silicon dioxide formed by standard chemical deposition bonding technique. The microstructure 10 of a semiconductor device, for example, is subjected to the analysis which measures the layer 18 which crosses the surface 20. A thickness profile data is determined with such an apparatus as an oval polarimeter. The thickness profile map of the thick coating material layer 18 is used so as to form a residence time versus position map. A plasma assisted chemical etching tool is controlled, in accordance with the dwell time versus position map to remove a material from a water while a surface 22 exposed with plasma etching forms the basis of the next manufacture processing.
Inventors:
PIITAA BII MUMORA
Application Number:
JP28375394A
Publication Date:
August 18, 1995
Filing Date:
November 17, 1994
Export Citation:
Assignee:
HUGHES AIRCRAFT CO
International Classes:
H01L21/302; H01L21/304; H01L21/3065; H01L21/3105; (IPC1-7): H01L21/3065; H01L21/304
Domestic Patent References:
| JPS62120029A | 1987-06-01 |
Foreign References:
| EP0514046A1 | 1992-11-19 |
Attorney, Agent or Firm:
Takehiko Suzue
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