PURPOSE: To evade malfunction to a circuit being the next stage of a bistable circuit by connecting the 1st MIS transistor (TR) and a gate in series with the 2nd MIS TR.

CONSTITUTION: The titled circuit is constituted by a circuit being the series connection of the 2nd N-channel MIS TR Q2 whose gate is connected to a clock F2 activating the circuit II of the next stage and the 1st N-channel MIS TR Q1 whose gate is connected is connected to the 2nd output terminal of the bistable circuit 1 between a power supply VSS and the 1st output terminal of the bistable circuit I receiving a signal A inputted asynchronously with signals F1, F2 activating the bistable circuit I and signals, B, C of the inversion of the signal A or logical 0. Thus, even when the input to the bistable circuit I is inputted asynchronously with the signal activating the bistable circuit I, no malfunction is caused to the circuit II of the next stage of the bistable circuit I.