Title:
MIS SEMICONDUCTOR MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JPS5440531
Kind Code:
A
Abstract:
PURPOSE: To reduce the power consumption of the memory array by applying the line or row selection signal to the gate of transmission MISFET.
Inventors:
SAITOU TAKESHI
ITOU TSUNEO
ITOU TSUNEO
Application Number:
JP10658777A
Publication Date:
March 30, 1979
Filing Date:
September 07, 1977
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/412; G11C11/419; (IPC1-7): G11C11/40