Title:
Mitigation of the abnormalities in a phase in the output signal of an analog to digital converter
Document Type and Number:
Japanese Patent JP6186611
Kind Code:
B2
Abstract:
A method and apparatus for mitigating a phase anomaly in an analogue-to-digital converter (ADC) output signal is disclosed. A plurality of codewords output by the ADC are received and information about an estimated level of interference due to the codeword is obtained for each codeword based on the logic values of bits in the codeword. In-phase (I) and quadrature (Q) corrections are obtained based on the information about the estimated level of interference, and applied to I and Q values obtained from the ADC output signal. The information about the estimated level of interference can be obtained based on the Hamming weight of the codeword, a weighted digit sum of the codeword, and the numbers of 0 to 1 and 1 to 0 transitions between the current codeword and the preceding codeword. In an embodiment, the information about the estimated level of interference can be a sequence of values defining an estimated interfering signal, and scaling and rotating the estimated interfering signal according to predetermined amplitude scaling and phase rotation parameters.
Inventors:
Louis Fargia
Mark Gibson
Ryan Pearson
Mark Gibson
Ryan Pearson
Application Number:
JP2015502302A
Publication Date:
August 30, 2017
Filing Date:
March 26, 2013
Export Citation:
Assignee:
AIRBUS DEFENCE AND SPACE LIMITED
International Classes:
H03M1/08
Domestic Patent References:
| JP10505471A | ||||
| JP4365821B2 | ||||
| JP11163826A |
Foreign References:
| US7266161 |
Attorney, Agent or Firm:
Ikeda adult
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi