To provide a mode setting circuit enabling setting various kinds of time reducing modes, and also to provide a counter circuit using the mode setting circuit.

The mode setting circuit has a plurality of stages of flip-flops 13, 14 which are cascaded and triggered by a pulse signal supplied from the outside; and logic circuits 15-19 for computing the output signal of each of the plurality of stages of flip-flops to generate a plurality of kinds of mode signals.