Title:
MONITOR CIRCUIT FOR CACHE UPDATING FAULT
Document Type and Number:
Japanese Patent JP01154265
Kind Code:
A
Abstract:
PURPOSE: To realize the reuse of caches and to improve the efficiency of a system by detecting automatically an unable updating state of cache data that is caused an error of data showing the old-new relation among cache data in the inter-cache data direction.
CONSTITUTION: An error recovery circuit 207 consists of gates 218, 219 and 220W225 and a data input/output circuit 226. When a gate output FO is selected, bit data (aWf) are all reset. Then these data (aWf) are updated and recovered by the selected outputs of the gates 218W225. In such a way, the data (aWf) are initially reset or recovered automatically in case either one of those data (aWf) has an error by some reasons and a loop is formed among cache data.
Inventors:
Ogawa, Shuzo
Application Number:
JP1987000314756
Publication Date:
June 16, 1989
Filing Date:
December 10, 1987
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F12/12; G06F12/12; (IPC1-7): G06F12/12
Previous Patent: DYNAMIC CHANNEL ADDRESS CONVERSION SYSTEM FOR VIRTUAL COMPUTER SYSTEM
Next Patent: PROTECTING DEVICE FOR INPUT/OUTPUT MEMORY SPACE
Next Patent: PROTECTING DEVICE FOR INPUT/OUTPUT MEMORY SPACE