Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MONITOR CIRCUIT FOR ERROR RATE
Document Type and Number:
Japanese Patent JPS5676664
Kind Code:
A
Abstract:

PURPOSE: To avoid the effect of phase shift of carrier, by providing a high pass filter in the circuit of Gooding which monitors the error rate of QPSK transmission system.

CONSTITUTION: QPSK signal is multiplied with carrier through 90°C hybrid at multipliers 100, 101 and fed to an operation circuit 105 via low pass filters 103, 104. The output sin(θ+α0) and sin(θ-α0) of the operating circuit 105 are multiplied and fed to the multiplier 109, the result is multiplied with sin2θ. Further, the outputs cos(θ+α0) and cos(θ-α0) and are multipled and the result is fed to a multiplier 110. The result is multiplied with sin2θ, and the outputs of the multipliers 109, 110 are mutually multiplied via high pass filters 111, 112. By adding the multiplied signal to the identification circuit 114, the error rate can be monitored. The α0 above is phase difference.


Inventors:
KURIHARA HIROSHI
TAKENAKA SADAO
Application Number:
JP15454979A
Publication Date:
June 24, 1981
Filing Date:
November 29, 1979
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H04L27/00; H04L27/233; (IPC1-7): H04L27/00; H04L27/22