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Title:
MONITOR CIRCUIT FOR RECEPTION INPUT LEVEL
Document Type and Number:
Japanese Patent JPH0442627
Kind Code:
A
Abstract:

PURPOSE: To obtain a monitor voltage changing linearly corresponding to a reception input level by providing a synthesizing circuit synthesizing the outputs of an IF detection amplifier section and an AGC voltage, inverting amplifier section, and extracting the output of the synthesizing circuit as a monitor voltage.

CONSTITUTION: The IF AGC output of an AGC amplifier circuit is detected by an IF signal detection amplifier section 10 and amplified and its output is fed to a synthesis circuit 12. An AGC voltage outputted from the AGC control circuit of the AGC amplifier circuit is inversely amplified by an AGC voltage inverting amplifier section 11 and the resulting signal is fed to the synthesizer 12. When the two voltages are synthesized by the synthesizer 12, an output voltage in which a change in a monitor voltage against the fluctuation of a reception input level almost linearly changes is obtained in all reception input level ranges. Thus, the characteristic in the reception input level versus monitor voltage is a characteristic almost close to a linear characteristic in all the reception input levels.


Inventors:
KIYONO HIDEKI
Application Number:
JP15043090A
Publication Date:
February 13, 1992
Filing Date:
June 08, 1990
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04B17/00; H04B17/318; (IPC1-7): H04B17/00
Attorney, Agent or Firm:
Akira Yamatani



 
Next Patent: JPH0442628