Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MONITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS63269636
Kind Code:
A
Abstract:

PURPOSE: To detect an error of standby high-order group signal and to monitor an active multiplex section at the sane time by allowing for a demultiplex circuit to convert a high-order group signal and a synchronizing pulse from a selection circuit into an output low-order group signal and allowing for a comparator circuit to apply bit comparision between the input low-order group signal and the output low-order group signal thereby discriminating the presence of the error.

CONSTITUTION: When a standby high-order group signal is inputted from a standby transmission line, frame synchronization is established by a synchronizing/decoding circuit 31 and error detection is applied and the standby high-order group signal (c) and the synchronizing pulse (d) are outputted to a selection circuit 32. The selection circuit 32, in the monitor state, selects a pair from the active high-order group signals a1∼a3 and the synchronizing pulses b1∼b2 from n-set of multiplex circuits 11∼21 and sends the result to a demultiplex circuit 33, which demultiplexes the high-order group signal and the synchronizing pulse selected in this way into the output low-order group signal. The output low-order group signal from the demultiplex circuit 33 and the input low-order group signal to the multiplex sections 1∼2 are subject to bit comparison by a comparator circuit 4. Thus, the error in the standby high-order group signal is detected and the n-set of the active multiplexer sections 1, 2 are monitored.


Inventors:
KONO OSAMU
Application Number:
JP10307287A
Publication Date:
November 07, 1988
Filing Date:
April 28, 1987
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H04J3/14; H04B17/00; (IPC1-7): H04B17/00; H04J3/14
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)