PURPOSE: To evade the generation of an event continuing repeated outputs and to quickly attain the restart of system operation by forcedly resetting hardware at the time of repeatedly outputting an interruption signal.

CONSTITUTION: An interruption signal I1 outputted when a watchdog timer 2 whose count value is cleared at a previously set fixed period is counted up, is stored in a register 5. When the timer 2 is counted up again in the stored state of the signal I1 in the register 5 and outputs the signal I1, a reset processing part 6 forcedly resets a system for clearing the counting of the timer 2. Since the timer 2 is not cleared at its counting, the generation of an event repeatedly outputting the signal I1 can be evaded.