Title:
モノリシック集積周波数復調回路
Document Type and Number:
Japanese Patent JP4026879
Kind Code:
B2
Abstract:
The circuit has a capacitor (20) which is charged at constant current to integrate of the height of each edge during a time period at maximum equal to half the period corresponding to the maximum frequency. The circuit has two symmetrical transistors (6,7). The input of a unitary gain separator is connected at a common node (19) with the capacitor and a constant current generator (18). The emitters are connected in common to a current generator (22) to form an output (21) to the circuit. A current switching circuit (24) comprising a similar differential structure may be placed on the output.
More Like This:
| WO/1993/010596 | DIGITAL DEMODULATOR |
| JPS54101651 | FM DEMODULATOR CIRCUIT |
Inventors:
Claude Clavlier
Xavier Giton
Xavier Giton
Application Number:
JP35144696A
Publication Date:
December 26, 2007
Filing Date:
December 27, 1996
Export Citation:
Assignee:
THOMSON BROADCAST SYSTEMS
International Classes:
H03D3/04; H03D3/14; H03K9/06
Domestic Patent References:
| JP4266206A | ||||
| JP56040306A | ||||
| JP63193710A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Toshiomi Yamazaki
Takuya Kuno