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Title:
MONOLITHIC MOS-SC CIRCUIT
Document Type and Number:
Japanese Patent JPH10126223
Kind Code:
A
Abstract:

To appropriately design the values of a settling time, mutual conductance, and capacitance by constituting the circuit by using a specific operational amplifier and a specific on-chip clock oscillator.

Two circuit has an operational amplifier, an on-chip clock oscillator which generates a clock signal, a capacitor K0, and a switch S0, and while the device operates through the operational amplifier clocked with the clock signal, the capacitor K0 is charged or discharged through it. Then a resistor and a frequency collaborative determination oscillator resistor, which determine the cutoff (dark) current and stationary current of the operational amplifier, are both actualized as the on-resistance of a MOS transistor which operates in a permanently conductive state. In the case of, for example, a current control clock oscillator, a resistor is a CMOS current mirror and includes a series circuit of transistors P1 and N1 and transistors P2 and N2.


Inventors:
SEESINK PETRUS H
Application Number:
JP26985397A
Publication Date:
May 15, 1998
Filing Date:
October 02, 1997
Export Citation:
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Assignee:
ENDRESS HAUSER GMBH CO
ENVEC MESS UND REGELTECHN GMBH
GRIESHABER VEGA KG
KAVLICO CORP
International Classes:
H03H19/00; H03K3/02; (IPC1-7): H03K3/02
Attorney, Agent or Firm:
Toshio Yano (2 outside)



 
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