PURPOSE: To speed up by reducing the substrate capacitance, and to stabilize the action by a method wherein miniaturization is attained by unnecessitating mask margins by self-alignment.

CONSTITUTION: Polycrystalline Si wirings 115 and 116 make contacts with each of source region made of a shallow junction 107 and a deep N+ diffused layer 111 and the drain region made of a shallow N+ diffused layer 108 and a deep junction 112 in self-alignment with a gate electrode 104. This unnecessitates margins for positioning and then enables the improvement in integration by markedly reducing the areas of the source and drain regions. Further, the flow of current becomes uniform because of uniform connection of the polycrystalline Si wirings 115 and 116 to the deep N+ diffused layers 111 and 112 in the width direction of the gate electrode 104, and the variability in stability and characteristics of the element is small. Moreover, the capacitance between the source and drain regions and the Si substrate 101 reduces, and the operating speed of the element markedly improves.