PURPOSE: To reduce the threshold voltage for channel formation by reducing the effective impurity concentration in the channel forming area.

CONSTITUTION: A (p+) area 4 is formed by B ion implanting thermal diffusion from the surface of the (n-) layer 1 of a silicon substrate composed of an (n+) layer 2 and an (n-) layer 1. Then, a (p) base area 3 is formed by B ion implanting thermal diffusion. As ion implanting thermal treatment is performed on a surface layer 15 which is to be the channel forming area in the (p) base area 3 so as to be activated. A gate oxide film 9 is formed, polycrystal line silicon is accumulated on the film 9 and a gate electrode 8 is formed by patterning. Then, B ion implanting thermal treatment is performed and a (p+) base area 5 is formed. In such a case, even when the B concentration of the (p) base layer is approximately 7×1019/cm3, the resistance value of a channel forming area surface layer 15 increases by introducing boron at a concentration of approximately 3×1019/cm3 into the channel forming area surface layer 15 and the threshold voltage is regulated at 4V or below.