Title:
MOUNTING METHOD FOR SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JPH01176679
Kind Code:
A
Abstract:
PURPOSE:To make the construction strong against the stress resulting from the difference between coefficients of thermal expansions so as to exactly prevents such phenomena that the connection pert breaks by making the shapes of the pad patterns of a printed board and the output terminals on the element chip side in rectangles arranged along radial lines streatching outward from the center of an element chip. CONSTITUTION:The shapes of pad patterns 12 on the printed board 20 side and output terminals 2 on the element chip 1 side are formed in rectangles which have the centers on the lattice lines in the checker shape and are arranged along the radial lines K stretching outward from the center O of the formation of the output terminals 2. By arranging the output terminals 2 and the pad patterns 12 like this, even if difference of coefficient of thermal expansion has arised between the printed board 20 and the element chip 1 at the time of bonding or element heat generation, a metal pipe connecting both works its bonding force effectively in the direction of the stress and remarkably high limit can be obtained.
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Inventors:
YAMAMOTO TAKESHI
Application Number:
JP97088A
Publication Date:
July 13, 1989
Filing Date:
January 05, 1988
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01R43/02; H05K1/11; H05K3/34; (IPC1-7): H01R43/02
Attorney, Agent or Firm:
Sadaichi Igita