Title:
MOUNTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
Document Type and Number:
Japanese Patent JPH01162344
Kind Code:
A
Abstract:
PURPOSE:To execute efficiently the mounting of a semiconductor chip onto a circuit board by a method wherein conductive grains are adhered on the conductor coupling part of the chip using a bonding agent and this adhered part is superposed on the conductor part of the board to heat and to fix by pressure both of the chip and the board. CONSTITUTION:A bonding agent layer 23, which is provided extendedly on a coupling part 13 of a wring 12 on a semiconductor integrated circuit chip 11, is formed. Then, conductive grains 41 are adhered on a part, which corresponds to the above-mentioned part 13, of the aforesaid layer 23 using a mask 31. Then, after this chip 11 is superposed on a circuit board 1 in such a way that the aforesaid grains 41 are positioned on a coupling part 3 of a wiring 2 formed on the board 1, both are heated and are fixed by pressure. According to such a way, the mounting of the chip 11 onto the board 1 can be executed in a short time and efficiently.
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Inventors:
WADA TSUTOMU
TAKAHASHI MINORU
TAKAHASHI MINORU
Application Number:
JP32218887A
Publication Date:
June 26, 1989
Filing Date:
December 18, 1987
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H01L21/60; H05K3/10; H05K3/32; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Shoji Tanaka