Title:
MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND INSPECTION METHOD THEREFOR
Document Type and Number:
Japanese Patent JP3848723
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent strains induced in a solder bump from being concentrated, so that a solder bump joint is improved in reliability by a method, wherein the bumps are provided, and only fine voids of nearly uniform size are present at an interface between all the bumps nearest the outer edge of a semiconductor device and the semiconductor device.
SOLUTION: A semiconductor element 4 is bonded to a ball-grid array board 2, and the ball-grid array board 2 is electrically connected to the semiconductor element 4 with a wire 5, which are sealed up with sealing resin 6. On the other hand, solder bumps 1 are bonded as an outer terminal to the rear of a ball-grid array semiconductor device, and the ball-grid array semiconductor device is mounted on a mounting board 3. Only uniform and fine voids are present at a joint interface 7 of the solder bumps 1. By this setup, strains induced in the solder bumps 1 at a thermal transformation time is restrained from concentrating on a part of the bump 1, so that a solder bump joint can be surely improved in connection reliability.
Inventors:
Makoto Kitano
Honda Michiharu
Honda Michiharu
Application Number:
JP7956997A
Publication Date:
November 22, 2006
Filing Date:
March 31, 1997
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L21/60; H01L21/66; H01L23/498; H05K3/34; H05K1/02; (IPC1-7): H01L21/60; H01L21/66
Domestic Patent References:
| JP7288255A | ||||
| JP9321172A | ||||
| JP8274211A | ||||
| JP88259A | ||||
| JP6323824A | ||||
| JP5259249A |
Attorney, Agent or Firm:
Manabu Inoue