Title:
MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2021040065
Kind Code:
A
Abstract:
To provide a mounting structure of a semiconductor device with which it is possible to reduce the self-inductance of the semiconductor device.SOLUTION: The mounting structure of a semiconductor device comprises: a semiconductor device B10 including a plurality of wiring boards 21 having a principal plane 21A, a semiconductor element 30 joined to one of the plurality of wiring boards 21, and a sealing resin having a top face 50A facing the same side as the principal plane 21A and covering the semiconductor element 30 for at least each portion of the plurality of wiring boards 21; a wiring board 60 facing the top face 50A; and a plurality of main terminals 61 for establishing electrical continuity between the plurality of wiring boards 21 and the wiring board 60. Each of the plurality of main terminals 61 is stretchable due to elastic deformation, and the sealing resin 50 has a plurality of first holes 51 leading from the top face 50A to the principal plane 21A. The plurality of main terminals 61 are individually inserted into the plurality of first holes 51, the tip of each of the plurality of main terminals 61 being pressed against the principal plane 21A of one of the plurality of wiring boards 21.SELECTED DRAWING: Figure 12
Inventors:
KANDA SOUZU
Application Number:
JP2019160959A
Publication Date:
March 11, 2021
Filing Date:
September 04, 2019
Export Citation:
Assignee:
ROHM CO LTD
International Classes:
H01L25/07; H01L25/18; H05K1/14; H05K1/18; H05K3/28
Domestic Patent References:
| JP2007184315A | 2007-07-19 | |||
| JP2014123618A | 2014-07-03 | |||
| JP2017204570A | 2017-11-16 | |||
| JP2004179492A | 2004-06-24 |
Foreign References:
| WO2008090734A1 | 2008-07-31 | |||
| WO2018043535A1 | 2018-03-08 |
Attorney, Agent or Firm:
Minoru Yoshida
Nao Usui
Nao Usui