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Patent Searching and Data


Title:
MPEG VIDEO DECODER CIRCUIT AND METHOD FOR ACTUALIZING REDUCTION OF MEMORY
Document Type and Number:
Japanese Patent JPH1098723
Kind Code:
A
Abstract:

To provide a video decoder circuit and a method which reduce the capacity of a memory for storing a video image.

This video decoder 1000 has an input buffer 1050 which receives an encoded and compressed data stream, a purging circuit 1060 which removes video header information from the data stream, a circuit 1090 which decodes the data stream, a circuit 1120 which decompresses the data stream, a circuit 1170 which selects a specific part of a previously selected frame, a memory 1025 which stores the decompressed data stream and the selected part of the previously selected frame, and a circuit 1180 which reconstitutes the selected part of the previously selected frame.


Inventors:
LACZKO FRANK L
CHIANG YETUNG PAUL
Application Number:
JP23494097A
Publication Date:
April 14, 1998
Filing Date:
August 29, 1997
Export Citation:
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Assignee:
TEXAS INSTRUMENTS INC
International Classes:
H04N5/907; G06T9/00; H03M7/30; H04N7/26; H04N7/36; H04N7/50; H04N5/14; H04N5/445; (IPC1-7): H04N7/24; H03M7/30; H04N5/907
Attorney, Agent or Firm:
Akira Asamura (3 outside)