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Patent Searching and Data


Title:
MULTI-BIT SUCCESSIVE APPROXIMATION ADC
Document Type and Number:
Japanese Patent JP2013093850
Kind Code:
A
Abstract:

To provide an analog/digital converter (ADC) which performs conversion into bits more than one per cycle, throughout several successive approximation cycles.

A system comprises a capacitive sub DAC circuit 410 and an approximator 430. A switch S2 isolates the capacitive sub DAC circuit during one or more first cycles and merges the sub DAC circuit during one or more final cycles. A successive approximation register (SAR) 440 generates a digital output signal or a DAC digital signal. Furthermore, the system includes a DAC circuit and pre-charges an input capacitor Cin with at least either analog input signals or DAC analog signals. A programmable gain amplifier 420 amplifies an error signal, a multi-bit ADC converts the amplified error signal into a multi-bit digital signal, and the SAR uses the multi-bit digital signal to generate a DAC digital signal or a digital output signal.


Inventors:
Olivier, Nys
Ark-chew, Wong
Application Number:
JP2012000235128
Publication Date:
May 16, 2013
Filing Date:
October 05, 2012
Export Citation:
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Assignee:
SEMTECH CORP
International Classes:
H03M1/46
Attorney, Agent or Firm:
辻居 幸一
熊倉 禎男
大塚 文昭
西島 孝喜
須田 洋之
上杉 浩