Title:
MULTI-FEED COMPLEX TRANSISTOR
Document Type and Number:
Japanese Patent JP3105654
Kind Code:
B2
Abstract:
PURPOSE: To prevent an abnormality, such as a shift in output level or an oscillation observed in the vicinity of saturation of power operation in a multi-feed high-output GaAs MESFET.
CONSTITUTION: A high resistance region is formed by implanting boron ions into parts other than a channel part. After a device-isolation step is carried out, an ohmic contact made up of Au/Ni/AuGe for a source electrode 14 and a drain electrode 16 is formed in a vapor deposition and lift-off method. Then, the channel is put in recess etching at two steps into a desired form, and an aluminum gate electrode 12 is formed in a vapor deposition and lift-off method. Finally, by Au plating, a power feeding electrode is formed, and a gate pad 13, and a drain pad 17 are formed.
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Inventors:
Naotaka Iwata
Application Number:
JP21806492A
Publication Date:
November 06, 2000
Filing Date:
August 18, 1992
Export Citation:
Assignee:
NEC
International Classes:
H01L27/06; H01L21/338; H01L21/8232; H01L29/417; H01L29/812; (IPC1-7): H01L21/338; H01L21/06; H01L21/8232; H01L29/812; H01L29/872
Domestic Patent References:
| JP1179459A | ||||
| JP494137A | ||||
| JP1181574A | ||||
| JP62293781A | ||||
| JP61172376A | ||||
| JP5162979A | ||||
| JP50159978A | ||||
| JP61104674A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)