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Patent Searching and Data


Title:
MULTI-LAYER PRINTED CIRCUIT BOARD PATTERN DESIGN PROCESSOR
Document Type and Number:
Japanese Patent JPH10222546
Kind Code:
A
Abstract:

To plot via on a display screen so that layers that are connected by via may intuitively and easily be decided in a printed circuit board pattern design processor.

A processing part 2 reads position data of via on a layer, layers connecting data and prescribed shape data from a storing part 3. The prescribed shape is divided into layer sections D1 to D6 which correspond to each layer and shown at a position of a display part 4 which corresponds to the position data, and also, via section V that corresponds to layers which are connected by via based on the layers connecting data, synthesized and shown. Furthermore, plural sections V that exist at the same display position are combined and shown.


Inventors:
KONNO EIICHI
KUMADA TORU
Application Number:
JP1942497A
Publication Date:
August 21, 1998
Filing Date:
January 31, 1997
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H05K3/46; G06F17/50; (IPC1-7): G06F17/50; H05K3/46
Attorney, Agent or Firm:
Shuji Moizumi