To provide a circuit for generating virtual multi-level output pulses for a class-D amplifier, where the time-voltage-area corresponds to a multiple of digital levels.
The disclosed invention includes a means for converting an input signal into an ideal PDM output pulse, a means 31 for generating a "pulse polarity" signal and a digital "pulse length select" signal representing a plurality of pulse range values, a means for determining a set of output pulse range reference values unique for each of stages of multi-level outputs, a pulse length integrator 32 for determining a pulse stop time on the basis of a pulse start time, the digital "pulse length select" signal and the output pulse range reference values, and a pulse generator 33 for using a pulse start signal and a pulse stop signal to impart the multi-level output pulses to a power driver. Further, the present invention is equipped with a means 34 for a class-D power driver that is controlled by a control pulse of the power driver to be voltage-driven with an output load using voltage, and a means 35 for the output load as an output target of the class-D amplifier.
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Fumitoshi Nishiyama