Title:
MULTI-LEVEL INVERTER
Document Type and Number:
Japanese Patent JP3262495
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a multi-level inverter that can suppress snubber loss properly and has at least four-level output using a clamp snubber circuit.
SOLUTION: DC input terminals are indicated by 1A-1D, an AC output terminal is indicated by 2, positive-side inverse continuity switches are indicated by 3A-3C, and negative-side continuity switches are indicated by 4A-4D. By fuming on or off each continuity switch, the AC output terminal 2 can generate a four-level potential that is equivalent to the potential of four DC input terminals. The maximum application voltage of each inverse continuity switch can be clamped by the maximum terminal voltage of each corresponding clamp snubber capacitor, thus suppressing surge voltage and reducing the loss of a snubber circuit.
Inventors:
Shinji Sato
Application Number:
JP13979896A
Publication Date:
March 04, 2002
Filing Date:
June 03, 1996
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H02M1/00; H02M7/48; H02M7/483; (IPC1-7): H02M7/48; H02M1/00
Domestic Patent References:
| JP4359679A | ||||
| JP5276760A | ||||
| JP89656A | ||||
| JP7194131A | ||||
| JP5227763A |
Attorney, Agent or Firm:
Hideaki Togawa
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